Semiconductor storage device

ABSTRACT

A semiconductor storage device  1  according to an aspect includes a first memory area  11 _ 1  and a second memory area  11 _ 2 . Memory cells MC_m_n and bit lines BL 1 , BL 2 _, . . . , BLm_ are disposed in a boundary area  18  between the first and second memory areas  11 _ 1  and  11 _ 2 . The memory cells MC_m_n disposed in the boundary area  18  includes memory cells into which no data is written, and a line  56  is formed in a place that overlaps memory cells disposed in the boundary area  18  when the boundary area  18  is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/807,957 filed on Jul. 24, 2015, which is a Continuation of U.S.application Ser. No. 14/082,320 filed on Nov. 18, 2013, which is basedupon and claims the benefit of priority from Japanese patent applicationNo. 2012-258669, filed on Nov. 27, 2012, the disclosures of which areincorporated herein in their entirety by reference.

BACKGROUND

The present invention relates to a semiconductor storage device, and inparticular to a semiconductor storage device including a plurality ofmemory areas.

In recent years, capacities of semiconductor storage devices such asDRAMs (Dynamic Random Access Memories) are becoming larger and larger.As a result, it is necessary to increase the integration densities ofmemory cell arrays in order to increase the capacities and reduce thecosts even further.

Japanese Unexamined Patent Application Publication No. 10-303389discloses a technique for effectively increasing the current capacity orthe number of power-supply lines or signal lines, and thereby forimproving the performance of peripheral circuits and/or the flexibilityof wiring layout design. Japanese Unexamined Patent ApplicationPublication No. 2001-210100 discloses a technique relating to asemiconductor storage device capable of detecting a failure in a dummycell or on a dummy word line, and thereby improving the productivity.

SUMMARY

The present inventors have found the following problem. As explainedabove in the BACKGROUND section, the capacities of semiconductor storagedevices are becoming larger and larger. As a result, it is necessary toincrease the integration densities of memory cell arrays in order toincrease the capacities and reduce the costs even further. To increasethe capacity, it is necessary to increase the current capacity ofpower-supply lines or signal lines. However, there is a problem that ifa new wiring area is provided to enhance power-supply lines or signallines, the chip becomes larger in size.

Other problems to be solved as well as novel features will be moreapparent from the following description and the accompanying drawings.

A first aspect of the present invention is a semiconductor storagedevice including a first memory area and a second memory area. A memorycell and a bit line are disposed in a boundary area between the firstand second memory areas. The memory cell disposed in the boundary areaincludes a memory cell into which no data is written, and a line isformed in a place that overlaps the memory cell disposed in the boundaryarea when the boundary area is viewed from the top.

According to the above-described aspect, it is possible to provide asemiconductor storage device capable of increasing the integrationdensity of a memory cell array and providing a line in the memory cellarray.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, advantages and features will be moreapparent from the following description of certain embodiments taken inconjunction with the accompanying drawings, in which:

FIG. 1 shows a configuration of a semiconductor storage device accordingto a first embodiment;

FIG. 2A shows one of unit memory cell arrays that form a semiconductorstorage device according to a first embodiment;

FIG. 2B is a circuit diagram showing an example of a memory cell;

FIG. 3 shows a configuration of a semiconductor storage device accordingto a first embodiment;

FIG. 4 shows a configuration of a semiconductor storage device accordingto a comparative example;

FIG. 5 shows a configuration of a semiconductor storage device accordingto a comparative example;

FIG. 6 shows a configuration of a semiconductor storage device accordingto a comparative example; and

FIG. 7 shows a configuration of a semiconductor storage device accordingto a second embodiment.

DETAILED DESCRIPTION First Embodiment

A first embodiment is explained hereinafter with reference to thedrawings. FIG. 1 shows a configuration of a semiconductor storage deviceaccording to a first embodiment. As shown in FIG. 1, in thesemiconductor storage device 1 according to this embodiment, a pluralityof memory mats 11 to 14 (each of which is represented by dots) aredisposed on a substrate 10. Power-supply trunk lines 15_1 to 15_4 aredisposed on the periphery of the memory mats 11 to 14. The power-supplytrunk lines 15_1 to 15_4 are electrically connected with each other. Thepower-supply trunk lines 15_1 to 15_4 are lines for supplying electricpower to each of the memory mats 11 to 14. The power-supply trunk lines15_1 to 15_4 are supplied with electric power from a power-supplyline(s) disposed in another wiring layer(s) (not shown) through vias17_1 to 17_4.

Further, a power-supply line 16 that electrically connects thepower-supply trunk line 15_1 with the power-supply trunk line 15_2 isdisposed between the power-supply trunk lines 15_1 and 15_2. Thepower-supply line 16 is disposed so as to pass through the center ofeach of the memory mats 11 to 14. That is, the memory mat 11 includes amemory area 11_1 and a memory area 11_2, and the power-supply line 16 isdisposed so as to pass between the memory areas 11_1 and 11_2.Similarly, the memory mats 12 to 14 include memory areas 12_1 to 14_1respectively and memory areas 12_2 to 14_2 respectively, and thepower-supply line 16 is disposed so as to pass between the memory areas12_1 to 14_1 and the memory areas 12_2 to 14_2.

Further, a plurality of power-supply lines 21_1 for supplying electricpower to the memory area 11_1 are disposed in a place corresponding tothe memory area 11_1. The power-supply lines 21_1 are electricallyconnected to the power-supply trunk line 15_3 and the power-supply line16. Similarly, a plurality of power-supply lines 21_2 for supplyingelectric power to the memory area 11_2 are disposed in a placecorresponding to the memory area 11_2. The power-supply lines 21_2 areelectrically connected to the power-supply trunk line 15_4 and thepower-supply line 16. Further, power-supply lines 22_1 to 24_1 and 22_2to 24_2 are disposed for the other memory areas 12_1 to 14_1 and 12_2 to14_2 in a similar manner.

FIG. 2A shows one of the unit memory cell arrays that constitute thesemiconductor storage device according to this embodiment. Each of thememory mats 11 to 14 shown in FIG. 1 includes a plurality of unit memorycell arrays shown in FIG. 2A.

As shown in FIG. 2A, a unit memory cell array 31 (hereinafter, alsoreferred to simply as “memory cell array”) includes a plurality ofmemory cells MC_1_1 to MC_m_n, a plurality of bit lines BL1_, BL2, . . ., BLm, and a plurality of word lines WL1 to WLn. Each of the pluralityof memory cells MC_1_1 to MC_m_n is disposed in a place at which one ofthe bit lines intersects one of the word lines. Note that m and n arearbitrary natural numbers. The number m corresponds to the number of bitlines, and the number n corresponds to the number of word lines. In thisexample, the number of memory cells disposed in the unit memory cellarray 31 is expressed as “m×n”.

The plurality of bit lines BL1_, BL2, . . . , BLm are connected to senseamplifier groups 33 and 34 disposed on both sides of the unit memorycell array 31. A pair of bit lines BL1 and BL1_ are connected to bothsides of a sense amplifier SA1, and the memory cells MC_1_1 to MC_1_n ofthe unit memory cell array 31 are connected to the bit line BL_.

The semiconductor storage device 1 according to this embodiment is anopen bit-line type semiconductor storage device in which bit lines aredisposed on both sides of sense amplifiers. In this specification, ofthe bit line pair BLm, the bit line disposed on the left side of thesense amplifier SAm is referred to as “BLm” and the bit line disposed onthe right side of the sense amplifier SAm is referred to as “BLm_”.

Further, as shown in FIG. 2A, the odd-numbered sense amplifier groups 33and the even-numbered sense amplifier groups 34 are arranged in amutually staggered manner (i.e., alternately arranged). That is, thememory cells MC_1_1 to MC_1_n disposed in the first row of the unitmemory cell array 31 are connected to the odd-numbered sense amplifierSA1. The memory cells MC_2_1 to MC_2_n disposed in the second row of theunit memory cell array 31 are connected to the even-numbered senseamplifier SA2. The memory cells MC_3_1 to MC_3_n disposed in the thirdrow of the unit memory cell array 31 are connected to the odd-numberedsense amplifier SA3.

As described above, the memory cells disposed in the odd-numbered rowsof the unit memory cell array 31 are connected to the odd-numbered senseamplifiers SA1, SA3, . . . , SAm−1 and the memory cells disposed in theeven-numbered rows are connected to the even-numbered sense amplifiersSA2, SA4, . . . , SAm. With this configuration, the sense amplifiers SA1to SAm can be arranged in a mutually staggered manner.

Further, the plurality of word lines WL1 to WLn are connected to aword-line drive circuit WD disposed on the periphery of the unit memorycell array 31. Each of the memory cells MC_1_1 to MC_m_n includes, forexample, one transistor and one capacitor. FIG. 2B is a circuit diagramshowing an example of such a memory cell. As shown in FIG. 2B, thememory cell MC_1_1 includes a transistor Tr11 and a capacitor C11. Theword line WL1 is connected to the gate of the transistor Tr11. The bitline BL1_ is connected to the drain of the transistor Tr11. The sourceof the transistor Tr11 is connected to one end of the capacitor C11 andthe other end of the capacitor C11 is connected to a low-potential sidepower-supply voltage VSS. Each of the other memory cells has a similarconfiguration. Note that the configuration of one of the unit memorycell arrays constituting the semiconductor storage device, shown in FIG.2A is a mere example. For example, the arrangement of the senseamplifiers and the word-line drive circuit can be changed as desired.

In the unit memory cell array 31 shown in FIG. 2A, for example, whendata is written into the memory cell MC_1_1, the sense amplifier SA1raises or lowers the potential of the bit line BL1_ to a high level or alow level according to the data to be written. For example, whenhigh-level data “1” is written into the memory cell MC_1_1, the senseamplifier SA1 raises the potential of the bit line BL1_ to a high level(high-potential side power-supply voltage VDD). On the other hand, whenlow-level data “0” is written into the memory cell MC_1_1, the senseamplifier SA1 lowers the potential of the bit line BL1_ to a low level(low-potential side power-supply voltage VSS).

Further, the word-line drive circuit WD brings the word line WL1 into anactive state (for example, high level) and thereby turns on thetransistor Tr11 of the memory cell MC_1_1. As a result, the bit lineBL1_ is electrically connected to the capacitor C11 of the memory cellMC_1_1, and the capacitor C11 is thereby charged to the potentialcorresponding to the potential of the bit line BL1_. After that, theword-line drive circuit WD brings the word line WL1 into an inactivestate (for example, low level) and thereby turns off the transistor Tr11of the memory cell MC_1_1. By the operation like this, the capacitor C11of the memory cell MC_1_1 stores high-level data or low-level data.

The data written into the memory cell MC_1_1 in the above-describedmanner can be read in the following manner. Firstly, the sense amplifierSA1 pre-charges the bit line pair BL1 and BL1_ to a predeterminedvoltage. After that, the word-line drive circuit WD brings the word lineWL1 into an active state and thereby turns on the transistor Tr11 of thememory cell MC_1_1. As a result, the bit line BL1_ is electricallyconnected to the capacitor C11 of the memory cell MC_1_1 and thepotential (pre-charge voltage) of the bit line BL1_ changes according tothe potential (the amount of accumulated electrical charge) of thecapacitor C11. By detecting and amplifying this potential change of thebit line BL1_ by the sense amplifier SA1, the data written into thememory cell MC_1_1 can be determined. In this process, the potential ofthe bit line BL1 is used as a reference potential when the potential ofthe bit line BL1_ is detected. In other words, the bit line BL1 is usedto generate a reference signal when the sense amplifier SA1 reads datafrom the memory cell MC_1_1. Similarly, when data is read from orwritten into a memory cell connected to the bit line BL1, the bit lineBL1_ serves as a reference bit line.

Next, a configuration in the vicinity of the power-supply line 16 of thesemiconductor storage device 1 according to this embodiment is explainedwith reference to FIG. 3. Although the following explanation is made byusing the configuration of the memory mat 11 as an example, thefollowing explanation can be also applied to the configuration of eachof the other memory mats 12 to 14.

As shown in FIG. 3, each of the memory areas 11_1 and 11_2 includessense amplifiers SA1 to SAm and memory cells MC_1_1 to MC_m_n disposedon both sided of the sense amplifiers SA1 to SAm. Further, each of thememory areas 11_1 and 11_2 includes bit line pairs BL1 to BLm and BL1_to BLm_ that are connected to the memory cells MC_1_1 to MC_m_n and alsoconnected to the sense amplifiers SA1 to SAm respectively on both sidesof the sense amplifiers SA1 to SAm. That is, a plurality of unit memorycell arrays shown in FIG. 2A are disposed in each of the memory areas11_1 and 11_2.

As shown in FIG. 3, a memory cell array 51_1 and a memory cell array51_3 disposed in the memory area 11_1 (first memory area) are arrangedside by side in the direction parallel to the word lines WL1 to WLn.Further, the memory cell arrays 51_1 and 51_3 are disposed so as to besandwiched between a sense amplifier group 53_1 and a sense amplifiergroup 53_2. The word lines WL1 to WLn of the memory cell array 51_1 areconnected to a word-line drive circuit WD_1. The word lines WL1 to WLnof the memory cell array 51_3 are connected to a word-line drive circuitWD_3.

Further, a line 55_1 is formed in a place corresponding to the memorycell arrays 51_1 and 51_3. The line 55_1 is formed in a different layerfrom the layer in which the memory cell arrays 51_1 and 51_3 are formed.For example, the line 55_1 is formed in a wiring layer that is formedabove the layer in which the word lines WL1 to WLn and the bit lines BL1to BLm and BL1_ to BLm_ are formed. The line 55_1 is formed so as topass through the memory mats 11 to 14. For example, the line 55_1 is asignal line for supplying a word-line drive signal to the word-linedrive circuits WD_1 and WD_3 (i.e., a plurality of word-line drivecircuits arranged in the direction parallel to the word lines WL1 toWLn).

Similarly, a memory cell array 51_2 and a memory cell array 51_4disposed in the memory area 11_1 are arranged side by side in thedirection parallel to the word lines WL1 to WLn. Further, the memorycell arrays 51_2 and 51_4 are disposed so as to be sandwiched between asense amplifier group 53_2 and a sense amplifier group 53_3. The wordlines WL1 to WLn of the memory cell array 51_2 are connected to aword-line drive circuit WD_2. The word lines WL1 to WLn of the memorycell array 51_4 are connected to a word-line drive circuit WD_4.

Further, a line 55_2 is formed in a place corresponding to the memorycell arrays 51_2 and 51_4. The line 55_2 is formed in a different layerfrom the layer in which the memory cell arrays 51_2 and 51_4 are formed.For example, the line 55_2 is formed in a wiring layer that is formedabove the layer in which the word lines WL1 to WLn and the bit lines BL1to BLm and BL1_ to BLm_ are formed. The line 55_2 is formed so as topass through the memory mats 11 to 14. For example, the line 55_2 is asignal line for supplying a word-line drive signal to the word-linedrive circuits WD_2 and WD_4 (i.e., a plurality of word-line drivecircuits arranged in the direction parallel to the word lines WL1 toWLn).

Memory cell arrays 51_5 and 51_7 and memory cell arrays 51_6 and 51_8disposed in the memory area 11_2 (second memory area) are configured ina similar manner to the memory cell arrays disposed in the memory area11_1. Similarly to the above-described configuration, a line 55_3 isformed in a place corresponding to the memory cell arrays 51_5 and 51_7.The line 55_3 is formed in a different layer from the layer in which thememory cell arrays 51_5 and 51_7 are formed. Similarly, a line 55_4 isformed in a place corresponding to the memory cell arrays 51_6 and 51_8.The line 55_4 is formed in a different layer from the layer in which thememory cell arrays 51_6 and 51_8 are formed.

Further, memory cell arrays 51_9 and 51_10 are disposed in a memory cellarray end section in which the memory area 11_1 and the memory area 11_2adjoin each other. The memory cell arrays 51_9 and 51_10 are arranged inside by side in the direction parallel to the word lines WL1 to WLn.Further, the memory cell arrays 51_9 and 51_10 are disposed so as to besandwiched between a sense amplifier group 53_3 and a sense amplifiergroup 53_4.

In the boundary area 18 in which the memory cell arrays 51_9 and 51_10are disposed, bit lines BL2_, BL4_, . . . , BLm_ (the bit lines BL2_,BL4_, . . . , BLm_ are connected to the memory area 11_2 side (rightside in the figure) of respective sense amplifiers of the senseamplifier group 53_3) and memory cells MC_2_n, MC_4_n, . . . , MC_m_nare disposed. Further, in the boundary area 18, bit lines BL1, BL3, . .. , BLm−1 (the bit lines BL1, BL3, . . . , BLm−1 are connected to thememory area 11_1 side (left side in the figure) of respective senseamplifiers of the sense amplifier group 53_4) and memory cells MC_1_n,MC_3_n, . . . , MC_m−1_n are disposed (for the symbols, see also FIG.2A).

The word lines WL1 to WLn of the memory cell arrays 51_9 and 51_10disposed in the boundary area 18 are configured so that they are kept inan inactive state at all operation modes. Therefore, no data is writteninto each memory cell of the memory cell arrays 51_9 and 51_10 disposedin the boundary area 18. For example, the word lines WL1 to WLn of thememory cell arrays 51_9 and 51_10 can be kept in an inactive state atall operation modes by electrically connecting the word lines WL1 to WLnto a low-potential side power-supply line. Alternatively, the word linesWL1 to WLn of the memory cell arrays 51_9 and 51_10 may be connected toa word-line drive circuit (not shown) and thereby brought into aninactive state by using the word-line drive circuit (not shown). Forexample, the word lines WL1 to WLn of the memory cell arrays 51_9 and51_10 can be brought into an inactive state by electrically connectingthe word lines WL1 to WLn to a low-potential side power-supply line byusing the word-line drive circuit. By keeping the word lines WL1 to WLnof the memory cell arrays 51_9 and 51_10 in an inactive state at alloperation modes, the transistors constituting the memory cells can bekept in an off-state at all operation modes, and thus making it possibleto prevent any data from being written into the memory cells.

That is, the bit lines BL1, BL2_, . . . , BLm_ of the memory cell arrays51_9 and 51_10 disposed in the array end section of the memory cellarrays constituting the memory areas 11_1 and 11_2 are connected to thesense amplifiers SA1 to SAm. Therefore, the bit lines BL1, BL2_, . . . ,BLm_ are used to generate reference signals when the sense amplifiersSA1 to SAm read data from the memory cell arrays 51_2, 51_4, 51_5 and51_7.

For example, when data written into the memory cell MC_1_1 of the memorycell array 51_5 is read, the sense amplifier SA1 pre-charges the bitline BL1 disposed in the memory cell array 51_9 of the boundary area 18and the bit line BL1_ disposed in the memory cell array 51_5 of thememory area 11_2 to a predetermined potential. After that, a word-linedrive circuit WD_5 brings the word line WL1 into an active state andthereby turns on the transistor of the memory cell MC_1_1. As a result,the bit line BL1_ is electrically connected to the capacitor of thememory cell MC_1_1 and the potential (pre-charge voltage) of the bitline BL1_ changes according to the potential (the amount of accumulatedelectrical charge) of the capacitor. By detecting and amplifying apotential difference between this bit line BL1_ and the bit line BL1 ofthe boundary area 18 by the sense amplifier SA1, the data written intothe memory cell MC_1_1 can be determined.

In this process, the potential of the bit line BL1 disposed in thememory cell array 51_9 of the boundary area 18 is used as a referencepotential when the potential of the bit line BL1_ disposed in the memorycell array 51_5 of the memory area 11_2 is detected.

Further, a line 56 (first line) is formed in a place corresponding tothe memory cell arrays 51_9 and 51_10 disposed in the boundary area 18.The line 56 is formed in a different layer from the layer in which thememory cell arrays 51_9 and 51_10 are formed. In other words, the memorycells disposed in the boundary area 18 include memory cells into whichno data is written. Further, the line 56 is formed in a place thatoverlaps the memory cells disposed in the boundary area 18 when theboundary area 18 is viewed from the top.

For example, the line 56 is formed in a wiring layer that is formedabove the layer in which the word lines WL1 to WLn and the bit lines BL1to BLm and BL1_ to BLm_ are formed. Note that no data is written intothe memory cell arrays 51_9 and 51_10 disposed in the boundary area 18.That is, the word lines WL1 to WLn of the memory cell arrays 51_9 and51_10 disposed in the boundary area 18 are configured so that they arekept in an inactive state at all operation modes. Therefore, the line 56does not need to be used as a signal line for driving any word-linedrive circuit WD. Further, the line 56 is formed so as to pass throughthe memory mats 11 to 14. Therefore, in the semiconductor storage device1 according to this embodiment, the line 56 can be used as thepower-supply line 16 shown in FIG. 1. For example, the line 56 can beformed in the layer at the same level as the lines 55_1 and 55_2 formedin the memory area 11_1 and the lines 55_3 and 55_4 formed in the memoryarea 11_2.

FIG. 4 shows a configuration of a semiconductor storage device 101according to a comparative example. As shown in FIG. 4, in thesemiconductor storage device 101, a plurality of memory mats 111 to 114(each of which is represented by dots) are disposed on a substrate 110.Power-supply trunk lines 115_1 to 115_4 are disposed on the periphery ofthe memory mats 111 to 114. The power-supply trunk lines 115_1 to 115_4are electrically connected with each other. The power-supply trunk lines115_1 to 115_4 are lines for supplying electric power to each of thememory mats 111 to 114. The power-supply trunk lines 115_1 to 115_4 aresupplied with electric power from a power-supply line(s) disposed inanother wiring layer(s) (not shown) through vias 117_1 to 117_4.

Further, power-supply lines 121 to 124 for supplying electric power tothe respective memory mats 111 to 114 are disposed in placescorresponding to the respective memory mats 111 to 114. The power-supplylines 121 to 124 are electrically connected to the power-supply trunklines 115_3 and 115_4. For this configuration, there has been a problemthat when the longitudinal length of the memory mats 111 to 114 islarge, the amount of supplied electrical power decreases in and near thecentral part 116 of the memory mats 111 to 114. In other words, therehas been a problem that when the power-supply lines 121 to 124 are long,the amount of supplied electrical power decreases in and near the centerof the power-supply lines 121 to 124.

Therefore, as shown in FIG. 1, it has been necessary to dispose thepower-supply line 16 in or near the central part of the memory mats 111to 114. Therefore, it is conceivable to divide the memory area of thememory cell array and to provide a new wiring area for disposing thepower-supply line 16 between the divided memory areas. However, therehas been a problem that the chip becomes larger in size.

Accordingly, in the semiconductor storage device 1 according to thisembodiment, the memory mat is divided into the memory areas 11_1 and11_2 and the divided memory areas 11_1 and 11_2 share the common arrayend (which corresponds to the boundary area 18). Further, a layerlocated above this shared array end is used as a wiring area. That is,the memory areas 11_1 and 11_2 share the common array end in theboundary area 18, and no data is written into memory cells disposed inthis boundary area 18. Consequently, since the line 56 does not need tobe used as a signal line for driving any word-line drive circuit WD, theline 56 can be used as the power-supply line 16 shown in FIG. 1.Therefore, the semiconductor storage device according to this embodimentmakes it possible to increase the integration density of the memory cellarray and provide an additional line in the memory cell array.

FIG. 5 shows a configuration of a semiconductor storage device accordingto a comparative example. The semiconductor storage device shown in FIG.5 includes a plurality of unit memory cell arrays explained above withreference to FIG. 2A. That is, each memory cell array includes aplurality of memory cells MC_1_1 to MC_m_n, a plurality of bit linesBL1_, BL2, . . . , BLm, and a plurality of word lines WL1 to WLn. Eachof the plurality of memory cells MC_1_1 to MC_m_n is disposed in a placeat which one of the bit lines intersects one of the word lines. Notethat m and n are arbitrary natural numbers. The number m corresponds tothe number of bit lines, and the number n corresponds to the number ofword lines. In this example, the number of memory cells disposed in theunit memory cell array 131 is expressed as “m×n”.

As shown in FIG. 5, in an open bit-line type memory cell array in whichsense amplifiers SA1 to SAm are alternately arranged, array ends 132 and133 are formed on both sides of a memory area 131. Note that bit linesthat are not connected to any sense amplifier are formed in the arrayends 132 and 133. That is, bit lines BL1_, BL3_, . . . , BLm−1_ are notconnected to any sense amplifier in the array end 132. Further, bitlines BL2, BL4, . . . , BLm are not connected to any sense amplifier inthe array end 133.

Further, in the semiconductor storage device shown in FIG. 5, when thememory area 131 is divided and a wiring area is formed between thedivided memory areas, the semiconductor storage device has aconfiguration shown in FIG. 6. That is, as shown in FIG. 6, when thememory area 131 is divided into areas 131_1 and 131_2, a memory area 141and an array end 142 are newly formed in the area 131_1 and a memoryarea 151 and an array end 152 are newly formed in the area 131_2.

Similarly to the above-described configuration, bit lines that are notconnected to any sense amplifier are formed in the array ends 142 and152. That is, bit lines BL2, BL4, . . . , BLm are not connected to anysense amplifier in the array end 142. Further, bit lines BL1_, BL3_, . .. , BLm−1_ are not connected to any sense amplifier in the array end152.

Further, when a new line 156 is provided in the memory area 131, theline 156 is disposed between the areas 131_1 and 131_2, i.e., betweenthe array ends 142 and 152. Therefore, when a line 156 having a width W1is provided, it is necessary to secure a width W2 that is obtained byadding up the width W1 of the line 156, the width of the array end 142,and the width of the array end 152. As a result, there has been aproblem that the memory cell array becomes larger in size.

Therefore, in the semiconductor storage device 1 according to thisembodiment, as shown in FIG. 3, the memory areas 11_1 and 11_2 sharetheir array end and a layer located above this shared array end is usedas a wiring area. That is, the memory areas 11_1 and 11_2 share thecommon array end in the boundary area 18, and no data is written intothe memory cells disposed in this boundary area 18. Consequently, sincethe line 56 does not need to be used as a signal line for driving anyword-line drive circuit WD, the line 56 can be used as the power-supplyline 16 shown in FIG. 1. Therefore, the semiconductor storage deviceaccording to this embodiment makes it possible to increase theintegration density of the memory cell array and provide an additionalline in the memory cell array.

Further, in the semiconductor storage device 1 according to thisembodiment, all the bit lines disposed in the boundary area 18 areconnected to the sense amplifiers SA1 to SAm. Therefore, when datawritten into a memory cell array adjacent to the boundary area 18 isread by using the sense amplifiers SA1 to SAm, the sense amplifiers SA1to SAm can generate a reference signal(s) by using a bit line(s)disposed in the boundary area 18. As a result, it is possible toeffectively use the bit lines disposed in the boundary area 18.

Note that in the above-explained semiconductor storage device 1according to this embodiment, a case where the line 56 is used as apower-supply line is explained. However, the line 56 may be used as asignal line other than the power-supply line. For example, the line 56may be used as a line for supplying a signal (e.g., test-mode signal)that is commonly used in each of the memory mats 11 to 14 (see FIG. 1).

Second Embodiment

Next, a second embodiment is explained. FIG. 7 shows a configuration ofa semiconductor storage device according to a second embodiment, andcorresponds to FIG. 3 in the first embodiment. The semiconductor storagedevice according to this embodiment is different from the semiconductorstorage device according to the first embodiment in that some of thememory cells disposed in the boundary area 18 are used as reserve memorycells. The semiconductor storage device according to this embodiment issubstantially the same as the semiconductor storage device according tothe first embodiment except for this difference. Therefore, the samesymbols are assigned to the same components and their duplicatedexplanation is omitted.

As shown in FIG. 7, memory cell arrays 51_9′ and 51_10′ are disposed inthe boundary area 18 between the memory areas 11_1 and 11_2. The memorycell arrays 51_9′ and 51_10′ are arranged side by side in the directionparallel to the word lines WL1 to WLn. Further, the memory cell arrays51_9′ and 51_10′ are disposed so as to be sandwiched between the senseamplifier groups 53_3 and 53_4.

Among the word lines 62 and 66 of the memory cell array 51_9′ disposedin the boundary area 18, the word lines 62 (third word lines) areconnected to a word-line drive circuit WD (third word-line drivecircuit). Therefore, data can be written into the memory cells (reservememory cells) 61 connected to the word lines 62. On the other hand,among the word lines 62 and 66 of the memory cell array 51_9′ disposedin the boundary area 18, the word lines 66 are kept in an inactive stateat all operation modes. Therefore, no data is written into the memorycells 65 connected to the word lines 66. The memory cell array 51_10′ isconfigured in a similar manner.

Further, the bit lines BL1, BL2_, . . . , BLm_ of the memory cell arrays51_9′ and 51_10′ disposed in the boundary area 18 are connected to thesense amplifiers SA1 to SAm. Therefore, the sense amplifiers SA1 to SAmcan write data into the memory cell 61 and read data stored in thememory cells 61.

Further, the bit lines BL1, BL2_, . . . , BLm_ are used to generatereference signals when the sense amplifiers SA1 to SAm read data fromthe memory cell arrays 51_2, 51_4, 51_5 and 51_7.

Further, a line 63 (third line) is formed in a place corresponding tothe reserve memory cells 61 of the memory cell arrays 51_9′ and 51_10′.The line 63 is formed in a different layer from the layer in which thememory cell arrays 51_9′ and 51_10′ are formed. For example, the line 63is formed in a wiring layer that is formed above the layer in which theword lines and the bit lines are formed. The line 63 is formed so as topass through the memory mats 11 to 14 (see FIG. 1). For example, theline 63 is a signal line for supplying a word-line drive signal toword-line drive circuits WD (i.e., a plurality of word-line drivecircuits arranged in the direction parallel to the word line 62).

Further, a line 64 (first line) is formed in a place corresponding tomemory cells 65 of the memory cell arrays 51_9′ and 51_10′. The line 64is formed in a different layer from the layer in which the memory cellarrays 51_9′ and 51_10′ are formed. That is, the line 64 is formed in aplace that overlaps the memory cells 65 into which no data is written.For example, the line 64 is formed in a wiring layer that is formedabove the layer in which the word lines and the bit lines are formed.The line 64 is formed so as to pass through the memory mats 11 to 14(see FIG. 1). The line 64 can be used as the power-supply line 16 shownin FIG. 1.

That is, in the semiconductor storage device according to thisembodiment, when it is unnecessary to form the line 64 used as thepower-supply line over the entire boundary area 18, i.e., when the line64 has enough capability as the power-supply line, the reserve memorycells 61 are provided in part of the boundary area 18. The reservememory cells 61 are memory cells that are used, when a failure(s) occursin a memory cell(s) disposed in the memory areas 11_1 and 11_2, as asubstitute for the failed memory cell(s). When the memory cells 61 areused, a word-line drive signal is supplied to the word-line drivecircuit WD through the line 63. By constructing the semiconductorstorage device with redundancy as described above, the reliability ofthe semiconductor storage device can be improved. Further, the boundaryarea 18 can be used without any waste.

As a typical example, the total number of the word lines 62 connected tothe reserve memory cells 61 and the word lines 66 connected to theunused memory cells 65 can be equal to the number n of the word lines ofthe unit memory cell arrays disposed in the memory areas 11_1 and 11_2.However, the number of the word lines 62 connected to the reserve memorycells 61 may be arbitrarily determined. That is, there are no particularrestrictions on the area other than the area in which the line 64 isdisposed. That is, an arbitrary number of memory cells 61 can bedisposed in that area.

Note that in this embodiment, a case where the line 64 is used as apower-supply line is also explained. However, the line 64 may be used asa signal line other than the power-supply line. For example, the line 64may be used as a line for supplying a signal (e.g., test-mode signal)that is commonly used in each of the memory mats 11 to 14 (see FIG. 1).

The present invention made by the inventors has been explained above ina specific manner based on embodiments. However, the present inventionis not limited to the above-described embodiments, and needless to say,various modifications can be made without departing from the spirit andscope of the present invention.

The first and second embodiments can be combined as desirable by one ofordinary skill in the art.

While the invention has been described in terms of several embodiments,those skilled in the art will recognize that the invention can bepracticed with various modifications within the spirit and scope of theappended claims and the invention is not limited to the examplesdescribed above.

Further, the scope of the claims is not limited by the embodimentsdescribed above.

Furthermore, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

What is claimed is:
 1. A semiconductor storage device, comprising: afirst and a second memory region, each of the first and second memoryregion including a plurality of memory cell array units; a first memorycell array unit in the first memory region having a plurality of firstsense amplifiers, a plurality of first bit line pairs extending bothsides of the first sense amplifiers, and a plurality of first memorycells connected to the first bit line pairs; a second memory cell arrayunit in the second memory region having a plurality of second senseamplifiers, a plurality of second bit line pairs extending both sides ofthe second sense amplifiers, and a plurality of second memory cellsconnected to the second bit line pairs; a first power supply linearranged to surround the first and second memory region; a second powersupply line extending in a word-line direction and being connected tothe first power supply line; wherein one of the first bit line pairs andone of the second bit line pairs are alternately provided in theword-line direction between the first and second sense amplifiers,wherein first word lines connected to the first memory cells and thesecond memory cells between the first and second sense amplifiers are inan inactivate state, and wherein the second power supply line is formedbetween the first and second sense amplifiers so as to overlap the firstand second memory cells between the first and second sense amplifiers inplane view.
 2. The semiconductor storage device according to claim 1,wherein the first word lines are in inactivate state at all operationmodes.
 3. The semiconductor storage device according to claim 1, whereinthe first word lines are connected to a low-potential side power-supplyline.
 4. The semiconductor storage device according to claim 1, whereinthe first and second memory cells disposed between the first and secondsense amplifiers further includes a plurality of reserve memory cellsused for replacement of a defective memory cell, the reserve memorycells are connected to second word lines different from the first wordlines.
 5. The semiconductor storage device according to claim 1, whereinthe first bit line pairs and the second bit line pairs provided betweenthe first and second sense amplifiers are used to generate a referencesignal when the first and second sense amplifiers read data from thefirst and second memory cells.